FPGA-Driven Parallel Inference Engine for High-Throughput Deep Learning in Autonomous Robotics

The general need to have energy-efficient and high-performance processing with edge-centric AI systems through the development of an energy-scaled RISC-V microarchitecture with custom instruction fusion. It is an architecture that combines fused micro-operations in convolution, dot-product, activation, and reduction with tensors, which is enabled by dynamic voltage-frequency scaling and execution control through workload consideration. The specified design was tested with the help of a multi-phase benchmark, which included CNN kernels, attention blocks with transformers, and real-Time inference loads. The experimental findings indicate that the execution latency is reduced by 32.8%, the switching activity is reduced by 41.3% and the overall energy consumption is reduced by 27.5% to that of the baseline core. The fused instruction engine is also able to enhance AI throughput by 1.82x, and the area overhead is less than 6%. The Hardware in the loop testing proved to be stable with different workload densities. Generally, the system provides a balanced architectural platform that provides improved computational efficiency, power-saving budgets, and scalable deployment in future-generation embedded intelligence systems.