A review on 3D Network on Chip: Architecture design and optimization of multi-core media applications

Buffering applications impose demanding baud rate and output guarantees in multicore processor. The two dimensional (2D) chip manufacturing technology is facing wire delay and power consumption challenges. Three Dimensional (3D) manufacturing technology reduces chip area significantly on System on Chips (SoC's), which in turn reduces latencies for interconnect structures and system throughput, performance, and power increases. An enhanced switching policy technique, Label switching Network on chip (LS NoC) had been implemented to improve throughput and bandwidth reservation for streaming applications in 2D NoC. Label switching technique utilizes lesser bits than the node identification numbers and provides better Quality of service than other switching techniques. This handout presents a review in the dwelling of Network on Chip in 2D and emphasis the major challenges faced in the design of 2D standard NoCs, by the research community. © 2016 IEEE.