Approximate Computing based Low Latency VLSI Architecture for Real Time Signal Processing

Real-time EEG signal processing is critical in brain-computer interface (BCI) systems, epilepsy monitoring, and cognitive state detection, but existing VLSI architectures struggle to balance speed, energy efficiency, and signal integrity. The paper introduces a new approximate computing, low latency VLSI architecture that is optimized to process continuous EEGs and based on stochastic number generators, biased truncation arithmetic, inexact SRAMs, and adaptive clock gating. The system is called AC-RTSPNet and it dynamically determines the computation precision depending on the sensitivity of the signal where it can make smart trade-offs between energy and accuracy. The proposed design was tested with the CHB-MIT Scalp EEG dataset (average latency of 4.3 μs, 44.2 mW) and was found to be more accurate at classifying (94.8) than SVM (90.5%), CNN (91.1%), and RNN (93.2%) baselines. Spectral fidelity had a correlation of more than 94% that was clinically relevant. Xilinx Zynq-7000 implementation of hardware showed a large saving of area and resource over precise hardware designs. The study indicates the usefulness of hybrid approximation techniques in constrained real-time. AC-RTSPNet is a reconfigurable and scalable domain-specific solution to wearable EEG devices and portable neural diagnostic devices, providing a new outlook to approximate VLSI frameworks in neuro-engineering.