An Efficient VLSI Design Model using Alpha-Beta Filtering and RTree-based Fast Preprocessing with Deep Reinforcement Learning Algorithm

A VLSI Design Model is an organised system for creating, simulating, and refining integrated circuits that have millions of transistors packed into a single chip. The Enhanced VLSI Automated Block Routing and Design (EVABRD) model constructs a system aimed at increasing the effectiveness of floor planning and routing in VLSI design. It entails three computational techniques: Deep Reinforcement Learning (DRL) for floor planning, R-Tree-based preprocessing for routing efficiency, and Alpha-Beta filtering for dynamic parameter management. The DRL unit models the design as a Markov Decision Process (MDP), which facilitates policy optimisation by successive interaction with the environment and receipt of rewards. The R-Tree method is used to be less redundant in localising the connections, while depth-first search and overlap checking are used to improve scheduling and routing methods. Alpha-Beta filtering facilitates the enhancement of tracking and the implementation of changes in design parameters dynamically. The performance analysis is cumulative probability, runtime, wirelength, Vout Vs Vout_Bar, and sensing delay.