P. Vimala

Usha, C. ., Vimala, P. ., Ramkumar, K. ., & Ramakrishnan, V. . (2022). Electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunnel field-effect transistor using the superposition principle. Journal of Computational Electronics, 21(1), 181-190. https://doi.org/10.1007/s10825-021-01819-z

Vimala, P. ., Haque, ul ., & Usha, C. . (2022). Modeling of Source Pocket Engineered PNPN Tunnel FET on High-K Buried Oxide (H-BOX) Substrate for Improved ON Current. Silicon, 14(16), 10383-10389. https://doi.org/10.1007/s12633-022-01778-5

Vimala, P. ., Dharshan, K. ., Harshith, S. ., Kishore, V. ., & Usha, C. . (2023). A Study of Graphene FET for Better Performance. Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/ICEEICT56924.2023.10157680

Usha, C. ., & Vimala, P. . (2023). Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages. In Tunneling Field Effect Transistors: Design, Modeling and Applications (pp. 99-123). CRC Press. https://doi.org/10.1201/9781003327035-6

Vimala, P. ., & Usha, C. . (2024). Impact of material in gate engineering of various TFET architectures. In Handbook of Emerging Materials for Semiconductor Industry (pp. 333-351). Springer Nature. https://doi.org/10.1007/978-981-99-6649-3_25